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K40P104M100SF2 k40 sub-family data sheet supports the following: mk40n512vll100, mk40n512v.l100 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 100 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb program flash memory on non- flexmemory devices C up to 128 kb ram C serial programming interface (ezport) ? clocks C 1 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C 10 low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 16-channel dma controller, supporting up to 64 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C hardware random-number generator C 128-bit unique identification (id) number per chip ? human-machine interface C segment lcd controller supporting up to 40 frontplanes and 8 backplanes, or 44 frontplanes and 4 backplanes C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C 16-bit sar adc with pga (x64) C 12-bit dac C analog comparator (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timers C two-channel quadrature decoder/general purpose timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C usb full-/low-speed on-the-go controller with on- chip transceiver C controller area network (can) module C spi modules C i2c modules C uart modules C secure digital host controller (sdhc) C i2s freescale semiconductor document number: K40P104M100SF2 data sheet: product preview rev. 1, 11/2010 this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. ? 2010C2010 freescale semiconductor, inc. preliminary preliminary
table of contents 1 ordering parts ...........................................................................4 1.1 determining valid orderable parts......................................4 2 part identification ......................................................................4 2.1 description.........................................................................4 2.2 format ...............................................................................4 2.3 fields .................................................................................4 2.4 example ............................................................................5 3 terminology and guidelines ......................................................5 3.1 definition: operating requirement......................................5 3.2 definition: operating behavior ...........................................6 3.3 definition: attribute ............................................................6 3.4 definition: rating ...............................................................7 3.5 result of exceeding a rating ..............................................7 3.6 relationship between ratings and operating requirements......................................................................7 3.7 guidelines for ratings and operating requirements............8 3.8 definition: typical value.....................................................8 3.9 typical value conditions ...................................................9 4 ratings ......................................................................................9 4.1 thermal handling ratings ...................................................9 4.2 moisture handling ratings .................................................. 10 4.3 esd handling ratings .........................................................10 4.4 voltage and current operating ratings ............................... 10 5 general ..................................................................................... 11 5.1 nonswitching electrical specifications ............................... 11 5.1.1 voltage and current operating requirements ...... 11 5.1.2 lvd and por operating requirements ................. 12 5.1.3 voltage and current operating behaviors .............. 13 5.1.4 power mode transition operating behaviors .......... 13 5.1.5 power consumption operating behaviors .............. 14 5.1.5.1 diagram: typical idd_run operating behavior...............................................16 5.1.6 emc radiated emissions operating behaviors.......17 5.1.7 designing with radiated emissions in mind ........... 18 5.1.8 capacitance attributes .......................................... 18 5.2 switching electrical specifications ..................................... 18 5.3 thermal specifications ....................................................... 18 5.3.1 thermal operating requirements ........................... 18 5.3.2 thermal attributes ................................................. 19 6 peripheral operating requirements and behaviors .................... 19 6.1 core modules .................................................................... 19 6.1.1 debug trace timing specifications ......................... 19 6.1.2 jtag electricals .................................................... 20 6.2 system modules ................................................................ 23 6.3 clock modules ................................................................... 23 6.3.1 mcg specifications...............................................23 6.3.2 oscillator electrical characteristics ....................... 25 6.3.2.1 oscillator dc electrical specifications 25 6.3.2.2 oscillator frequency specifications ...... 26 6.3.3 32khz oscillator electrical characteristics............27 6.3.3.1 32khz oscillator dc electrical specifications...................................... 27 6.3.3.2 32khz oscillator frequency specifications...................................... 27 6.4 memories and memory interfaces ..................................... 28 6.4.1 flash (ftfl) electrical characteristics ................. 28 6.4.1.1 flash timing parameters program and erase............................................ 28 6.4.1.2 flash timing parameters commands.......................................... 28 6.4.1.3 flash (ftfl) current and power parameters.......................................... 29 6.4.1.4 reliability characteristics .................... 29 6.4.2 ezport switching specifications ............................ 29 6.5 security and integrity modules .......................................... 30 6.6 analog ............................................................................... 30 6.6.1 adc electrical specifications ................................. 31 6.6.1.1 16-bit adc operating conditions..........31 6.6.1.2 16-bit adc electrical characteristics....33 6.6.1.3 16-bit adc with pga operating conditions............................................ 36 6.6.1.4 16-bit adc with pga characteristics ... 37 6.6.2 cmp and 6-bit dac electrical specifications ......... 38 6.6.3 12-bit dac electrical characteristics ..................... 39 6.6.3.1 12-bit dac operating requirements ..... 39 6.6.3.2 12-bit dac operating behaviors .......... 40 6.6.4 voltage reference electrical specifications..........42 6.7 timers................................................................................43 6.8 communication interfaces ................................................. 43 6.8.1 usb electrical specifications ................................. 44 k40 sub-family data sheet data sheet, rev. 1, 11/2010. 2 preliminary freescale semiconductor, inc. preliminary
6.8.2 usb dcd electrical specifications ....................... 44 6.8.3 usb voltage regulator electrical specifications .. 44 6.8.4 dspi switching specifications for low-speed operation.............................................................. 45 6.8.5 dspi switching specifications (high-speed mode).................................................................... 46 6.8.6 sdhc specifications ............................................. 48 6.8.7 i2s switching specifications ................................. 49 6.9 human-machine interfaces (hmi)......................................51 6.9.1 general switching specifications .......................... 51 6.9.2 tsi electrical specifications .................................. 52 6.9.3 lcd electrical characteristics ................................ 52 7 dimensions ............................................................................... 53 7.1 obtaining package dimensions ......................................... 54 8 pinout ........................................................................................ 54 8.1 k40 signal multiplexing and pin assignments .................. 54 8.2 k40 pinouts ....................................................................... 58 9 revision history ........................................................................ 59 k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 3 preliminary
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: pk40 and mk40. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## m fff t pp ccc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k40 m flash memory type ? n = program flash only ? x = program flash and flexmemory table continues on the next page... ordering parts k40 sub-family data sheet data sheet, rev. 1, 11/2010. 4 preliminary freescale semiconductor, inc. preliminary
field description values fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb t temperature range (c) ? v = C40 to 105 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? fx = 64 qfn (9 mm x 9 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? mb = 81 mapbga (8 mm x 8 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? ml = 104 mapbga (8 mm x 8 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) ? mf = 196 mapbga (15 mm x 15 mm) ? mj = 256 mapbga (17 mm x 17 mm) ccc maximum cpu frequency (mhz) ? 50 = 50 mhz ? 72 = 72 mhz ? 100 = 100 mhz ? 120 = 120 mhz ? 150 = 150 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mk40x256vmd100 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. terminology and guidelines k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 5 preliminary
3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply volt\ age 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digi\ tal pins 7 pf terminology and guidelines k40 sub-family data sheet data sheet, rev. 1, 11/2010. 6 preliminary freescale semiconductor, inc. preliminary
3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply volt\ age C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. terminology and guidelines k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 7 preliminary
3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range limited operating range - no permanent failure - possible decreased life - possible incorrect operation fatal range - probable permanent failure limited operating range - no permanent failure - possible decreased life - possible incorrect operation handling range - no permanent failure fatal range - probable permanent failure operating or handling rating (max.) operating requirement (max.) operating requirement (min.) operating or handling rating (min.) 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a terminology and guidelines k40 sub-family data sheet data sheet, rev. 1, 11/2010. 8 preliminary freescale semiconductor, inc. preliminary
3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings ratings k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 9 preliminary
4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 solder temperature, leaded 245 1. determined according to jedec standard jesd22-a103, high temperature storage life. 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 85c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm). 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components. 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 185 ma v dio digital input voltage (except reset, extal, and xtal) C0.3 5.5 v v aio analog, reset, extal, and xtal input voltage C0.3 v dd + 0.3 v table continues on the next page... ratings k40 sub-family data sheet data sheet, rev. 1, 11/2010. 10 preliminary freescale semiconductor, inc. preliminary
symbol description min. max. unit i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v i dda analog supply current 1 tbd tbd ma v usb_dp usb_dp input voltage C0.3 3.63 v v usb_dm usb_dm input voltage C0.3 3.63 v vregin usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file tbd v 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 5 general 5.1 nonswitching electrical specifications 5.1.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v table continues on the next page... general k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 11 preliminary
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i ic dc injection current single pin ? v in > v dd ? v in < v ss 0 0 2 C0.2 ma ma 1 dc injection current total mcu limit, includes sum of all stressed pins ? v in > v dd ? v in < v ss 0 0 25 C5 ma ma 1 1. all functional non-supply pins are internally clamped to vss and vdd. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. power supply must maintain regulation within operating vdd range during instantaneous and operating maximum current conditions. if positive injection current (vin > vdd) is greater than idd, the injection current may flow out of vdd and could result in external power supply going out of regulation. ensure external vdd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5.1.2 lvd and por operating requirements table 2. lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage tbd 1.1 tbd v v lvdh falling low-voltage detect threshold high range (lvdv=01) tbd 2.56 tbd v v lvw1 v lvw2 v lvw3 v lvw4 low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) tbd tbd tbd tbd 2.70 2.80 2.90 3.00 tbd tbd tbd tbd v v v v 1 v hys low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) tbd tbd tbd v v lvw1 v lvw2 v lvw3 v lvw4 low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) tbd tbd tbd tbd 1.80 1.90 2.00 2.10 tbd tbd tbd tbd v v v v 1 table continues on the next page... general k40 sub-family data sheet data sheet, rev. 1, 11/2010. 12 preliminary freescale semiconductor, inc. preliminary
table 2. lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v hys low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference tbd 1.00 tbd v t lpo internal low power oscillator period factory trimmed tbd 1000 tbd s 1. rising thresholds are falling threshold + v hys 5.1.3 voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = -10ma ? 1.71 v v dd 2.7 v, i oh = -3ma v dd C 0.5 v dd C 0.5 v v output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2ma ? 1.71 v v dd 2.7 v, i oh = -0.6ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 10ma ? 1.71 v v dd 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2ma ? 1.71 v v dd 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) 1 a i oz hi-z (off-state) leakage current (per pin) 1 a r pu and r pd internal weak pullup and pulldown resistors 30 50 k 1 1. measured at v il max and v dd min general k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 13 preliminary
5.1.4 power mode transition operating behaviors in the table below, all specifications except t por , assume the following clock configuration: ? cpu and system clocks = 100mhz ? bus clock = 50 mhz ? flash clock = 25 mhz table 4. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 run vlls1 run ? run vlls1 ? vlls1 run 4.1 123.8 s s run vlls2 run ? run vlls2 ? vlls2 run 4.1 49.3 s s run vlls3 run ? run vlls3 ? vlls3 run 4.1 49.2 s s run lls run ? run lls ? lls run 4.1 5.9 s s run stop run ? run stop ? stop run 4.1 4.2 s s run vlps run ? run vlps ? vlps run 4.1 5.8 s s 1. normal boot (ftfl_opt[lpboot]=1) general k40 sub-family data sheet data sheet, rev. 1, 11/2010. 14 preliminary freescale semiconductor, inc. preliminary
5.1.5 power consumption operating behaviors table 5. power consumption operating behaviors symbol description min. typ. max. unit notes i dd_run run mode current all peripheral clocks disa\ bled, code executing from flash ? @ 1.8v ? @ 3.0v 40 42 tbd tbd ma ma 1 i dd_run run mode current all peripheral clocks ena\ bled, code executing from flash ? @ 1.8v ? @ 3.0v 55 56 tbd tbd ma ma 2 i dd_run_m ax run mode current all peripheral clocks ena\ bled and peripherals active, code executing from flash ? @ 1.8v ? @ 3.0v 85 85 tbd tbd ma ma 3 i dd_wait wait mode current at 3.0 v all peripheral clocks disabled 15 tbd ma 4 i dd_stop stop mode current at 3.0 v 1.4 tbd ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.25 tbd ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled tbd tbd ma 6 i dd_vlpw very-low-power wait mode current at 3.0 v 1.05 tbd ma 7 i dd_vlps very-low-power stop mode current at 3.0 v 30 tbd a i dd_lls low leakage stop mode current at 3.0 v 12 tbd a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? 128kb ram devices 8 tbd a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v 4 tbd a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v 2 tbd a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v 550 tbd na 1. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 2. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, but peripherals are not in active operation. 3. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, and peripherals are in active operation. 4. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flash clock. mcg configured for fei mode. 5. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks disabled. code executing from flash. 6. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. general k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 15 preliminary
7. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks disabled. 5.1.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) ? all peripheral clocks disabled except ftfl ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash figure 1. run mode supply current vs. core frequency all peripheral clocks disabled the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) ? all peripheral clocks enabled but peripherals are not in active operation ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash general k40 sub-family data sheet data sheet, rev. 1, 11/2010. 16 preliminary freescale semiconductor, inc. preliminary
figure 2. run mode supply current vs. core frequency all peripheral clocks enabled 5.1.6 emc radiated emissions operating behaviors table 6. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 tbd dbv 1, 2 v re2 radiated emissions voltage, band 2 50C150 tbd v re3 radiated emissions voltage, band 3 150C500 tbd v re4 radiated emissions voltage, band 4 500C1000 tbd v re_iec_sae iec and sae level 0.15C1000 tbd 2, 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions, iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method, and sae standard j1752-3, measurement of radiated emissions from integrated circuitstem/ wideband tem (gtem) cell method. 2. v dd = 3 v, t a = 25 c, f osc = 16 mhz (crystal), f bus = 20 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method, and appendix d of sae standard j1752-3, measurement of radiated emissions from integrated circuitstem/wideband tem (gtem) cell method. general k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 17 preliminary
5.1.7 designing with radiated emissions in mind 1. to find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for emc design. 5.1.8 capacitance attributes table 7. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 5.2 switching electrical specifications table 8. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 100 mhz f bus bus clock 50 mhz f flash flash clock 25 mhz vlpr mode f sys system and core clock 2 mhz f bus bus clock 2 mhz f flash flash clock 1 mhz 5.3 thermal specifications general k40 sub-family data sheet data sheet, rev. 1, 11/2010. 18 preliminary freescale semiconductor, inc. preliminary
5.3.1 thermal operating requirements table 9. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 5.3.2 thermal attributes board type symbol description 104 mapbga 100 lqfp unit notes single- layer (1s) r ja thermal resistance, junction to ambient (natural convection) tbd tbd c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) tbd tbd c/w 1 single- layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) tbd tbd c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) tbd tbd c/w 1 r jb thermal resistance, junction to board tbd tbd c/w 2 r jc thermal resistance, junction to case tbd tbd c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) tbd tbd c/w 4 6 peripheral operating requirements and behaviors 6.1 core modules 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air), or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air). 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditions junction-to-board. 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 19 preliminary
6.1.1 debug trace timing specifications table 10. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 3. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 4. trace data specifications 6.1.2 jtag electricals table 11. jtag electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? jtag and cjtag ? serial wire debug 0 0 25 50 mhz j2 tclk cycle period 1/j1 ns table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 20 preliminary freescale semiconductor, inc. preliminary
table 11. jtag electricals (continued) symbol description min. max. unit j3 tclk clock pulse width ? jtag and cjtag ? serial wire debug 20 10 ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 30 ns j8 tclk low to boundary scan output high-z 30 ns j9 tms, tdi input data setup time to tclk rise 16 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 4 ns j12 tclk low to tdo high-z 4 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 5. test clock input timing peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 21 preliminary
j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 6. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 7. test access port timing peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 22 preliminary freescale semiconductor, inc. preliminary
j14 j13 tclk trst figure 8. trst timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules 6.3.1 mcg specifications table 12. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) facto\ ry trimmed at nominal vdd and 25c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz t irefsts internal reference (slow clock) startup time tbd 4 s fdco_res_t resolution of trimmed dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.1 0.3 %f dco f dco_res_t resolution of trimmed dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco f dco_t total deviation of trimmed dco output frequency over voltage and temperature + 0.5 - 1.0 3.5 %f dco f dco_t total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0C 70c 0.5 tbd %f dco f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 3.875 4 4.125 mhz f intf_t internal reference frequency (fast clock) user trimmed 3 5 mhz table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 23 preliminary
table 12. mcg specifications (continued) symbol description min. typ. max. unit notes t irefstf internal reference startup time (fast clock) tbd tbd s f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f dco_t dco output fre\ quency range user trimmed and dmx32=0 low range (drs=00) 640 f ints_t 20 20.97 25 mhz 1, 2 mid range (drs=01) 1280 f ints_t 40 41.94 50 mhz mid-high range (drs=10 192)0 f ints_t 60 62.91 75 mhz high range (drs=11) 2560 f ints_t 80 83.89 100 mhz f dco_t_dmx3 2 dco output fre\ quency range reference = 32,768hz and dmx32=1 low range (drs=00) 732 f ints_t 23.99 mhz 3 mid range (drs=01) 1464 f ints_t 47.97 mhz mid-high range (drs=10) 2197 f ints_t 71.99 mhz high range (drs=11) 2929 f ints_t 95.98 mhz j cyc_fll fll period jitter tbd tbd ps 4 j acc_fll fll accumulated jitter of dco output over a 1s time window tbd tbd ps t fll_acquire fll target frequency acquisition time 1 ms 5 pll f vco vco operating frequency 48.0 100 mhz f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter 400 ps 6, 7 j acc_pll pll accumulated jitter over 1s window tbd ps 6 , 7 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 0.15 + 1075(1/ f pll_ref ) ms 8 1. the resulting system clock frequencies should not exceed their maximum specified values. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 24 preliminary freescale semiconductor, inc. preliminary
2. this specification includes the 2% precision of the internal reference frequency (slow clock). 3. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 4. this specification was obtained at tbd frequency. 5. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 7. this specification was obtained at internal frequency of tbd. 8. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical characteristics this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 13. oscillator dc electrical specifications, (v ssosc = 0 v dc ) (t a = t l to t h ) symbol description min. typ. max. unit notes v dd33osc 3.3 v supply voltage 1.71 3.6 v i ddosc supply current low-power mode ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 500 100 200 300 700 1.2 1.5 na a a a a ma ma 1 i ddosc supply current high gain mode ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 25 200 400 800 1.5 3 4 a a a a ma ma ma 1 c x extal load capacitance 2, 3 c y xtal load capacitance 2 , 3 table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 25 preliminary
table 13. oscillator dc electrical specifications, (v ssosc = 0 v dc ) (t a = t l to t h ) (continued) symbol description min. typ. max. unit notes r f feedback resistor low-frequency, low-power mode m 2 , 3 feedback resistor low-frequency, high-gain mode 10 m feedback resistor high-frequency, low-power mode (1 C 8 mhz, 8 C 32 mhz) m feedback resistor high-frequency, high-gain mode (1 C 8 mhz, 8 C 32 mhz) 1 m r s series resistor low-frequency, low-power mode k series resistor low-frequency, high-gain mode 200 k series resistor high-frequency, low-power mode k series resistor high-frequency, high-gain mode ? 1 mhz resonator ? 2 mhz resonator ? 4 mhz resonator ? 8 mhz resonator ? 16 mhz resonator ? 20 mhz resonator ? 32 mhz resonator 6.6 3.3 0 0 0 0 0 k k k k k k k v pp peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode 0.75 v dd33osc v dd33osc v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode 0.75 v dd33osc v dd33osc v 1. v dd33osc =3.3 v, temperature =27 c, cx/cy=20 pf 2. see crystal or resonator manufacturer's recommendation 3. r f and c x ,c y are integrated in low-frequency, low-power mode and must not be attached externally peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 26 preliminary freescale semiconductor, inc. preliminary
6.3.2.2 oscillator frequency specifications table 14. oscillator frequency specifications, (v dd33osc = v dd33osc (min) to v dd33osc (max), t a = t l to t h ) symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) 1 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) 8 32 mhz t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal start-up time 32 khz low-frequency, low-power mode tbd ms 1, 2, 3 crystal start-up time 32 khz low-frequency, high-gain mode 800 ms crystal start-up time 8 mhz high-frequency, low-power mode 4 ms crystal start-up time 8 mhz high-frequency, high-gain mode 3 ms 1. this parameter is characterized before qualification rather than 100% tested. 2. proper pc board layout procedures must be followed to achieve specifications. 3. crystal start up time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32khz oscillator dc electrical specifications table 15. 32khz oscillator module dc electrical specifications (v ssosc = 0 v dc ) (t a = t l to t h ) symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 2.5 pf c load internal load capacitance (programmable) 15 pf v pp peak-to-peak amplitude of oscillation 0.6 v peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 27 preliminary
6.3.3.2 32khz oscillator frequency specifications table 16. 32khz oscillator frequency specifications (v dd33osc = v dd33osc (min) to v dd33osc (max), t a = t l to t h ) symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32 khz t start crystal start-up time 1000 ms 1, 2 1. this parameter is characterized before qualification rather than 100% tested. 2. proper pc board layout procedures must be followed to achieve specifications. 6.4 memories and memory interfaces 6.4.1 flash (ftfl) electrical characteristics this section describes the electrical characteristics of the ftfl module. 6.4.1.1 flash timing parameters program and erase the following characteristics represent the amount of time the internal charge pumps are active and do not include command overhead. table 17. nvm program/erase timing characteristics symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 20 tbd s t hversscr sector erase high-voltage time 20 100 ms 1 t hversblk erase block high-voltage time 160 800 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing parameters commands table 18. flash command timing characteristics symbol description min. typ. max. unit notes t rd1blk read 1s block execution time 1.4 ms t rd1sec2k read 1s section execution time (2 kb flash sec\ tor) 40 s t pgmchk program check execution time 35 s table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 28 preliminary freescale semiconductor, inc. preliminary
table 18. flash command timing characteristics (continued) symbol description min. typ. max. unit notes t rdrsrc read resource execution time 35 s 1 t pgm4 program longword execution time 50 tbd s t ersblk erase flash block execution time 160 800 ms 2 t ersscr erase flash sector execution time 20 100 ms 2 t pgmsec2k program section execution time (2 kb flash sec\ tor) tbd tbd ms t rd1all read 1s all blocks execution time 2.8 ms t rdonce read once execution time 35 s 1 t pgmonce program once execution time 50 tbd s t ersall erase all blocks execution time 320 1600 ms 2 t vfykey verify backdoor access key execution time 35 s 1 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 flash (ftfl) current and power parameters table 19. flash (ftfl) current and power parameters symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma 6.4.1.4 reliability characteristics table 20. nvm reliability characteristics symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 tbd years 2 t nvmretp1k data retention after up to 1 k cycles 10 tbd years 2 t nvmretp100 data retention after up to 100 cycles 15 tbd years 2 n nvmcycp cycling endurance 10 k tbd cycles 3 1. typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25c. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618. 2. data retention is based on t javg = 55c (temperature profile over the lifetime of the application). 3. cycling endurance represents number of program/erase cycles at -40c t j 125c peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 29 preliminary
6.4.2 ezport switching specifications table 21. ezport switching specifications num description min. max. unit operating voltage 2.7 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid (setup) 12 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 9. ezport timing diagram 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 30 preliminary freescale semiconductor, inc. preliminary
6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 22 and table 23 are achievable on the differential pins (adcx_dp0, adcx_dm0, adc, adcx_dp1, adcx_dm1, adcx_dp3, and adcx_dp3). the adcx_dp2 and adcx_dm2 adc inputs are used as the pga inputs and are not direct device pins. accuracy specifications for these pins are defined in table 24 and table 25. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 22. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd - v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss - v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl reference volt\ age low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capaci\ tance ? 16 bit modes ? 8/10/12 bit modes 8 4 10 5 pf r adin input resistance 2 5 k table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 31 preliminary
table 22. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes r as analog source resistance 16 bit modes ? f adck > 8mhz ? f adck = 4C8mhz ? f adck < 4mhz 13/12 bit modes ? f adck > 16mhz ? f adck > 8mhz ? f adck = 4C8mhz ? f adck < 4mhz 11/10 bit modes ? f adck > 8mhz ? f adck = 4C8mhz ? f adck < 4mhz 9/8 bit modes ? f adck > 8mhz ? f adck < 8mhz 0.5 1 2 0.5 1 2 5 2 5 10 5 10 k k k k k k k k k k k k external to mcu assumes adlsmp=0 f adck adc conversion clock frequency adlpc=0, adhsc=1 ? 16 bit modes ? 13 bit modes adlpc=0, adhsc=0 ? 16 bit modes ? 13 bit modes adlpc=1, adhsc=1 ? 16 bit modes ? 13 bit modes adlpc=1, adhsc=0 ? 16 bit modes ? 13 bit modes 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 tbd tbd 8.0 12.0 5.0 8.0 2.5 5.0 mhz mhz mhz mhz mhz mhz mhz mhz 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 32 preliminary freescale semiconductor, inc. preliminary
r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pininput pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 10. adc input impedance equivalency diagram 6.6.1.2 16-bit adc electrical characteristics table 23. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda supply current ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 215 340 470 610 a a a a adlsmp= 0 adco=1 supply current ? stop, reset, module off 0.01 0.8 a f adack adc asynchro\ nous clock source ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 tbd tbd tbd tbd 2.4 4.0 5.2 6.2 tbd tbd tbd tbd mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times conversion time see reference manual chapter for conversion times table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 33 preliminary
table 23. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes tue total unadjusted error ? 16 bit differential ? 16 bit single-ended ? 13 bit differential ? 12 bit single-ended ? 11 bit differential ? 10 bit single-ended ? 9 bit differential ? 8 bit single-ended 14.0 13.0 1.5 tbd 0.8 tbd 0.5 0.5 tbd tbd tbd tbd tbd tbd 1.0 1.0 lsb 3 max hard\ ware aver\ aging (avge = %1, avgs = %11) dnl differential non- linearity ? 16 bit differential ? 16 bit single-ended ? 13 bit differential ? 12 bit single-ended ? 11 bit differential ? 10 bit single-ended ? 9 bit differential ? 8 bit single-ended 2.5 2.5 0.7 0.7 0.5 tbd 0.2 0.2 tbd tbd tbd tbd tbd tbd 0.5 0.5 lsb 3 max hard\ ware aver\ aging (avge = %1, avgs = %11) inl integral non-line\ arity ? 16 bit differential ? 16 bit single-ended ? 13 bit differential ? 12 bit single-ended ? 11 bit differential ? 10 bit single-ended ? 9 bit differential ? 8 bit single-ended -6 to +2.5 -2 to +12 1.0 1.0 0.5 0.5 0.3 0.3 tbd tbd tbd tbd 0.5 0.5 lsb 3 max aver\ aging e zs zero-scale error ? 16 bit differential ? 16 bit single-ended ? 13 bit differential ? 12 bit single-ended ? 11 bit differential ? 10 bit single-ended ? 9 bit differential ? 8 bit single-ended 4.0 4.0 0.7 0.7 0.4 0.4 0.2 0.2 tbd tbd tbd tbd 0.5 0.5 lsb 3 v adin = v ssa table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 34 preliminary freescale semiconductor, inc. preliminary
table 23. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e fs full-scale error ? 16 bit differential ? 16 bit single-ended ? 13 bit differential ? 12 bit single-ended ? 11 bit differential ? 10 bit single-ended ? 9 bit differential ? 8 bit single-ended 0 to +10 0 to +14 1.0 tbd 0.4 0.4 0.2 0.2 tbd tbd tbd tbd 0.5 0.5 lsb 3 v adin = v dda e q quantization er\ ror ? 16 bit modes ? 13 bit modes -1 to 0 0.5 lsb 3 enob effective number of bits 16 bit differential mode ? avg=32 ? avg=16 ? avg=8 ? avg=4 ? avg=1 16 bit single-ended mode ? avg=32 ? avg=16 ? avg=8 ? avg=4 ? avg=1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 13.6 tbd 14.1 tbd 13.2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd bits bits bits bits bits bits bits bits bits bits 4 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 -94 tbd tbd tbd db db 4 sfdr spurious free dy\ namic range 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 tbd tbd 95 tbd db db 4 table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 35 preliminary
table 23. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e il input leakage er\ ror i in r as mv i in = leak\ age cur\ rent (refer to the mcu's voltage and cur\ rent oper\ ating rat\ ings) temp sensor slope ? C40c to 25c ? 25c to 105c tbd tbd mv/c mv/c v temp25 temp sensor voltage 25c tbd mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. 1 lsb = (v refh - v refl )/2 n 4. input data is 1 khz sine wave. 6.6.1.3 16-bit adc with pga operating conditions table 24. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vrefout vrefout vrefout v 2, 3 v adin input voltage v ssa v dda v r pga input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 tbd tbd tbd 64 32 16 tbd tbd tbd k r pgad differntial input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 tbd tbd tbd 128 64 32 tbd tbd tbd k in+ to in- r as analog source resistance gain = 16, 32 100 4 t s adc sampling time gain = 64 1.25 s 5 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vrefout) 3. pga reference connected to the vrefout pin. if the user wishes to drive vrefout with a voltage other than the output of the vref module, the vref module must be disabled. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 36 preliminary freescale semiconductor, inc. preliminary
4. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 5. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. the adlsts bits can be adjusted for different adc clock frequency 6.6.1.4 16-bit adc with pga characteristics table 25. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current tbd 590 tbd a i lkg leakage current pga disabled < 1 tbd a g gain 2 ? pgag=0 ? pgag=1 ? pgag=2 ? pgag=3 ? pgag=4 ? pgag=5 ? pgag=6 tbd tbd tbd tbd tbd tbd tbd 1 2 3.9 tbd tbd 29.9 tbd tbd tbd tbd tbd tbd tbd tbd db db db db db db db r as < 100 g a gain error 0.5 db r as < 100 bw input signal band\ width ? 16-bit modes ? < 16-bit modes 4 40 khz khz psrr power supply re\ jection ration gain=1 tbd tbd db v dda = 3v 100mv, f vdda = 50hz, 60hz cmrr common mode rejection ratio ? gain=1 ? gain=64 tbd tbd tbd tbd db db v cm = 500mvpp, f vcm = 50hz, 100hz v ofs input offset volt\ age 0.2 tbd mv gain=1, adc averaging=32 t gsw gain switching settling time tbd 10 s 3 dg/dt gain drift over temperature ? gain=1 ? gain=64 tbd tbd tbd tbd ppm/c ppm/c 0 to 50c dv ofs /dt offset drift over temperature gain=1 tbd tbd ppm/c 0 to 50c, adc averaging=32 dg/dv dda gain drift over supply voltage ? gain=1 ? gain=64 tbd tbd tbd tbd %/v %/v v dda from 1.71 to 3.6v table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 37 preliminary
table 25. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes e il input leakage er\ ror all modes i in r as mv i in = leakage current (refer to the mcu's voltage and current op\ erating ratings) v pp,diff maximum differ\ ential input signal swing [(v refpga 2.33) - 0.2] / (2 gain) v 4 snr signal-to-noise ratio ? gain=1 ? gain=64 tbd tbd 8.3 57.7 db db average=32 thd total harmonic distortion ? gain=1 ? gain=64 tbd tbd 87.3 85.3 db db average=32, f in =100hz sfdr spurious free dy\ namic range ? gain=1 ? gain=64 tbd tbd 92.42 92.54 db db average=32, f in =100hz enob effective number of bits ? gain=1, average=4 ? gain=1, average=8 ? gain=64, average=4 ? gain=64, average=8 ? gain=1, average=32 ? gain=2, average=32 ? gain=4, average=32 ? gain=8, average=32 ? gain=16, average=32 ? gain=32, average=32 ? gain=64, average=32 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 12.3 12.7 8.4 8.7 13.4 13.1 12.6 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits sinad signal-to-noise plus distortion ra\ tio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. gain = 2 pgagx 3. when the pga gain is changed, it takes some time to settle the output for the adc to work properly. during a gain switching, a few adc outputs should be discarded (minimum two data samples, may be more depending on adc sampling rate and time of the switching). 4. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 38 preliminary freescale semiconductor, inc. preliminary
6.6.2 cmp and 6-bit dac electrical specifications table 26. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1, vdda >= v lvi_trip ) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a i ddoff supply current, off mode (en=0,) 100 na v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis ? hystctr = 00 ? hystctr = 01 ? hystctr = 10 ? hystctr = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 120 ns t dls propagation delay, low-speed mode (en=1, pmode=1) 120 250 420 ns analog comparator initialization delay tbd ns i dac6b 6-bit dac current adder (enabled) 8 a inl 6-bit dac integral non-llnearity C0.5 0.5 lsb 1 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. 1 lsb = v reference /64 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 27. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.15 3.6 v 1 t a temperature ?40 105 c table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 39 preliminary
table 27. 12-bit dac operating requirements (continued) symbol desciption min. max. unit notes c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vrefo) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac 6.6.3.2 12-bit dac operating behaviors table 28. 12-bit dac operating behaviors symbol description min. typ. max. unit notes n resolution 12 12 b i dda_daclp supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low- power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high- power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode 5 s 1 t ccdachp code-to-code settling time (0xbf8 to 0xc08) high-speed mode 1 tbd s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 0 100 mv v dacouth dac output voltage range high high-speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 3 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 0.5 1 lsb 3 dnl differential non-linearity error v dacr = vre\ fo (1.15 v) 0.5 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage tbd v/c t ge temperature coefficient gain error tbd ppm of fsr/c a c offset aging coefficient tbd v/yr rop output resistance load = 3 k 250 table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 40 preliminary freescale semiconductor, inc. preliminary
table 28. 12-bit dac operating behaviors (continued) symbol description min. typ. max. unit notes sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0+100mv to vdacr?100 mv 3. the dnl is measured for 0+100 mv to v dacr ?100 mv 4. the dnl is measured for 0+100mv to v dacr ?100 mv with v dda > 2.4v 5. calculated by a best fit curve from v ss +100 mv to vref?100 mv figure 11. typical inl error vs. digital code peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 41 preliminary
figure 12. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 29. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature ?40 105 c c l output load capacitance 100 nf table 30. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim tbd 1.2 tbd v v out voltage reference output without factory trim 1.15 1.24 v v drift temperature drift (vmax -vmin across the full temperature range) 7 mv see fig\ ure 13 table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 42 preliminary freescale semiconductor, inc. preliminary
table 30. vref full-range operating behaviors (continued) symbol description min. typ. max. unit notes t c temperature coefficient tbd ppm/c ac aging coefficient tbd ppm/year i off powered down current (off mode, vrefen = 0, vrsten = 0) 0.10 a i bg bandgap only (mode_lv = 00) current tbd 75 a i tr tight-regulation buffer (mode_lv =10) current 1.1 ma load regulation (mode_lv = 10) current 100 v/ma t stup buffer startup time 100 tbd s dc line regulation (power supply rejection) tbd mv C60 tbd db table 31. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 32. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim tbd tbd a tbd figure 13. typical output vs.temperature tbd figure 14. typical output vs. vdd 6.7 timers see general switching specifications. 6.8 communication interfaces peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 43 preliminary
6.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. 6.8.2 usb dcd electrical specifications table 33. usb dcd specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) tbd tbd tbd v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 tbd 0.4 v 6.8.3 usb voltage regulator electrical specifications table 34. usb voltage regulator electrical specifications symbol description min. typ. max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero 120 a i ddstby quiescent current standby mode, load cur\ rent equal zero tbd a i ddoff quiescent current shutdown mode 500 na i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode tbd ma v reg33out regulator output voltage input supply (vre\ gin) > 3.6 v ? run mode ? standby mode ? pass-through mode 3 tbd 2.3 3.3 tbd 3.6 tbd 3.6 v v v 1 table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 44 preliminary freescale semiconductor, inc. preliminary
table 34. usb voltage regulator electrical specifications (continued) symbol description min. typ. max. unit notes c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series re\ sistance 1 100 m i lim current limitation threshold 185 290 395 ma 1. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.4 dspi switching specifications for low-speed operation the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 35. master mode dspi timing (low-speed mode) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bclk ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcsn to dspi_sck output valid (t sck /2) - 4 ns ds4 dspi_sck to dspi_pcsn output hold (t sck /2) - 4 ns ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -2 ns ds7 dspi_sin to dspi_sck input setup 15 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 45 preliminary
ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 15. dspi classic spi timing master mode table 36. slave mode dspi timing (low-speed mode) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bclk ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 5 ns ds14 dspi_sck to dsip_sin input hold 15 ns ds15 dspi_ss active to dspi_sout driven 15 ns ds16 dspi_ss inactive to dspi_sout not driven 15 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 16. dspi classic spi timing slave mode peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 46 preliminary freescale semiconductor, inc. preliminary
6.8.5 dspi switching specifications (high-speed mode) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 37. master mode dspi timing (high-speed mode) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bclk ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcsn to dspi_sck output valid (t sck /2) ? 2 ns ds4 dspi_sck to dspi_pcsn output hold (t sck /2) ? 2 ns ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid ?2 ns ds7 dspi_sin to dspi_sck input setup tbd ns ds8 dspi_sck to dspi_sin input hold 0 ns ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 17. dspi classic spi timing master mode table 38. slave mode dspi timing (high-speed mode) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 4 x t bclk ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2 + 2 ns ds11 dspi_sck to dspi_sout valid tbd ns table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 47 preliminary
table 38. slave mode dspi timing (high-speed mode) (continued) num description min. max. unit ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dsip_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 18. dspi classic spi timing slave mode 6.8.6 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 39. sdhc switching specifications num symbol description min. max. unit card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 48 preliminary freescale semiconductor, inc. preliminary
table 39. sdhc switching specifications (continued) num symbol description min. max. unit sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t thl sdhc input setup time 5 ns sd8 t thl sdhc input hold time 0 ns sd2 sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 19. sdhc timing 6.8.7 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 40. i 2 s master mode timing num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 2 x t sys ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 5 x t sys ns s4 i2s_bclk pulse width high/low 45% 55% bclk period table continues on the next page... peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 49 preliminary
table 40. i 2 s master mode timing (continued) num description min. max. unit s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid -2.5 ns s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid -3 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 20 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 20. i 2 s timing master mode table 41. i 2 s alave mode timing num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 8 x t sys ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 10 ns s14 i2s_fs input hold after i2s_bclk 3 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 10 ns s18 i2s_rxd hold after i2s_bclk 2 ns peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 50 preliminary freescale semiconductor, inc. preliminary
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 21. i 2 s timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 general switching specifications these general purpose specifications apply to all signals configured for gpio, sci, flexcan, cmt, and i 2 c signals. table 42. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disa\ bled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter disa\ bled, analog filter enabled) asynchronous path 100 ns 2 gpio pin interrupt pulse width (digital glitch filter disa\ bled, analog filter disabled) asynchronous path 16 ns 2 external reset pulse width (digital glitch filter disabled) tbd mode select ( ezp_cs) hold time after reset deasser\ tion 2 bus clock cycles port rise and fall time (high drive strength) ? slew disabled ? slew enabled 12 36 ns ns 3 port rise and fall time (low drive strength) ? slew disabled ? slew enabled 32 36 ns ns 4 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 51 preliminary
3. 75pf load 4. 15pf load 6.9.2 tsi electrical specifications table 43. touch sensing input module specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 5.5 tbd mhz f elemax electrode oscillator frequency 0.5 tbd mhz c ref internal reference capacitor tbd 1 tbd pf v delta oscillator delta voltage tbd 600 tbd mv i ref reference oscillator current source base current tbd 1 tbd a 2 i ele electrode oscillator current source base current tbd 1 tbd a 3 pres5 electrode capacitance measurement precision tbd tbd % 4 pres20 electrode capacitance measurement precision tbd tbd % 5 pres100 electrode capacitance measurement precision tbd tbd % 6 max\ sens20 max sensitivity @ 20pf electrode 0.15 0.326 600 ff 7 maxsens maximum sensitivity 0.006 0.326 24 ff 8 res resolution 16 bits t con20 response time @ 20pf 30 s 9 i tsi_run current added in run mode tbd a i tsi_lp low power mode current adder 1 tbd a 1. the tsi module is functional with capacitance values outside of this range. however, optimal performance is not guaranteed. 2. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current 3. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current 4. measured with a 5pf electrode, reference oscillator frequency of 10mhz, ps = 128, ncsc = 8; iext = 16 5. measured with a 20pf electrode, reference oscillator frequency of 10mhz, ps = 128, ncsc = 2; iext = 16 6. measured with a 20pf electrode, reference oscillator frequency of 10mhz, ps = 16, ncsc = 3; iext = 16 7. 6.2ms scan time 8. 1pf electrode capacitance with 4.96ms scan time 9. time that takes to do one complete measurement of the electrode. sensitivity resolution of 0.0133pf peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 1, 11/2010. 52 preliminary freescale semiconductor, inc. preliminary
6.9.3 lcd electrical characteristics table 44. lcd electricals symbol description min. typ. max. unit notes f frame lcd frame frequency 28 30 58 hz c lcd lcd charge pump capacitance nominal value 100 nf 1 c bylcd lcd bypass capacitance nominal value 100 nf 1 c glass lcd glass capacitance 2000 8000 pf v ireg v ireg hrefsel = 0 ? hrefsel = 0 ? hrefsel = 1 0.89 1.49 1.00 1.67 1.15 1.85 v v 2 rtrim v ireg trim resolution 3.0 % v ireg v ireg ripple ? hrefsel = 0 ? hrefsel = 1 30 50 mv mv i vireg v ireg current adder rven = 1 1 a 3 i rbias rbias current adder ? hrefsel = 0 ? hrefsel = 1 10 1 a a 3 r rbias rbias resistor values ? ladj = 00 or 01 low load (lcd glass capacitance 2000 pf) ? ladj = 10 or 11 high load (lcd glass capacitance 8000 pf) 0.28 2.98 m m vll2 vll2 voltage ? hrefsel = 0 ? hrefsel = 1 2.0 ? 5% 3.3 ? 5% 2.0 3.3 v v vll3 vll3 voltage ? hrefsel = 0 ? hrefsel = 1 3.0 ? 5% 5 ? 5% 3.0 5 v v 1. the actual value used could vary with tolerance. 2. v ireg maximum should never be externally driven to any level other than v dd - 0.15 v 3. 2000 pf load lcd, 32 hz frame frequency 7 dimensions dimensions k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 53 preliminary
7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 100-pin lqfp 98ass23308w 104-pin mapbga 98arh98267a 8 pinout 8.1 k40 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 100 qfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda 2 adc1_se5a adc1_se5a pte1 spi1_sout uart1_rx sdhc0_d0 i2c1_scl 3 adc1_se6a adc1_se6a pte2 spi1_sck uart1_cts_ b sdhc0_dclk 4 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_ b sdhc0_cmd 5 disabled pte4 spi1_pcs0 uart3_tx sdhc0_d3 6 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 7 disabled pte6 spi1_pcs3 uart3_cts_ b i2s0_mclk i2s0_clkin 8 vdd vdd 9 vss vss 10 usb0_dp usb0_dp 11 usb0_dm usb0_dm 12 vout33 vout33 13 vregin vregin 14 adc0_dp1 adc0_dp1 15 adc0_dm1 adc0_dm1 16 adc1_dp1 adc1_dp1 pinout k40 sub-family data sheet data sheet, rev. 1, 11/2010. 54 preliminary freescale semiconductor, inc. preliminary
100 qfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 17 adc1_dm1 adc1_dm1 18 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 19 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 20 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 21 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 22 vdda vdda 23 vrefh vrefh 24 vrefl vrefl 25 vssa vssa 26 vref_out vref_out 27 dac0_out dac0_out 28 xtal32 xtal32 29 extal32 extal32 30 vbat vbat 31 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx ewm_out_b 32 adc0_se18 adc0_se18 pte25 can1_rx uart4_rx ewm_in 33 disabled pte26 uart4_cts_ b rtc_clkout usb_clkin 34 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 35 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 36 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do 37 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_ b ftm0_ch0 jtag_tms/ swd_dio 38 nmi_b/ ezp_cs_b tsi0_ch5 pta4 ftm0_ch1 nmi_b ezp_cs_b 39 jtag_trst pta5 ftm0_ch2 cmp2_out i2s0_rx_bcl k jtag_trst 40 vdd vdd 41 vss vss 42 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 i2s0_txd ftm1_qd_ph a 43 cmp2_in1 cmp2_in1 pta13 can0_rx ftm1_ch1 i2s0_tx_fs ftm1_qd_ph b pinout k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 55 preliminary
100 qfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 44 disabled pta14 spi0_pcs0 uart0_tx i2s0_tx_bcl k 45 disabled pta15 spi0_sck uart0_rx i2s0_rxd 46 disabled pta16 spi0_sout uart0_cts_ b i2s0_rx_fs 47 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_ b i2s0_mclk i2s0_clkin 48 vdd vdd 49 vss vss 50 extal extal pta18 ftm0_flt2 ftm_clkin0 51 xtal xtal pta19 ftm1_flt0 ftm_clkin1 lpt0_alt1 52 reset_b reset_b 53 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 ptb0 i2c0_scl ftm1_ch0 ftm1_qd_ph a lcd_p0 54 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_ph b lcd_p1 55 lcd_p2/ adc0_se12/ tsi0_ch7 lcd_p2/ adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_ b ftm0_flt3 lcd_p2 56 lcd_p3/ adc0_se13/ tsi0_ch8 lcd_p3/ adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b ftm0_flt0 lcd_p3 57 lcd_p7/ adc1_se13 lcd_p7/ adc1_se13 ptb7 lcd_p7 58 lcd_p8 lcd_p8 ptb8 uart3_rts_ b lcd_p8 59 lcd_p9 lcd_p9 ptb9 spi1_pcs1 uart3_cts_ b lcd_p9 60 lcd_p10/ adc1_se14 lcd_p10/ adc1_se14 ptb10 spi1_pcs0 uart3_rx ftm0_flt1 lcd_p10 61 lcd_p11/ adc1_se15 lcd_p11/ adc1_se15 ptb11 spi1_sck uart3_tx ftm0_flt2 lcd_p11 62 lcd_p12/ tsi0_ch9 lcd_p12/ tsi0_ch9 ptb16 spi1_sout uart0_rx ewm_in lcd_p12 63 lcd_p13/ tsi0_ch10 lcd_p13/ tsi0_ch10 ptb17 spi1_sin uart0_tx ewm_out_b lcd_p13 64 lcd_p14/ tsi0_ch11 lcd_p14/ tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_bcl k ftm2_qd_ph a lcd_p14 65 lcd_p15/ tsi0_ch12 lcd_p15/ tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs ftm2_qd_ph b lcd_p15 66 lcd_p16 lcd_p16 ptb20 spi2_pcs0 cmp0_out lcd_p16 67 lcd_p17 lcd_p17 ptb21 spi2_sck cmp1_out lcd_p17 68 lcd_p18 lcd_p18 ptb22 spi2_sout cmp2_out lcd_p18 pinout k40 sub-family data sheet data sheet, rev. 1, 11/2010. 56 preliminary freescale semiconductor, inc. preliminary
100 qfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 69 lcd_p19 lcd_p19 ptb23 spi2_sin spi0_pcs5 lcd_p19 70 lcd_p20/ adc0_se14/ tsi0_ch13 lcd_p20/ adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg i2s0_txd lcd_p20 71 lcd_p21/ adc0_se15/ tsi0_ch14 lcd_p21/ adc0_se15/ tsi0_ch14 ptc1 spi0_pcs3 uart1_rts_ b ftm0_ch0 lcd_p21 72 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_ b ftm0_ch1 lcd_p22 73 lcd_p23/ cmp1_in1 lcd_p23/ cmp1_in1 ptc3 spi0_pcs1 uart1_rx ftm0_ch2 lcd_p23 74 vss vss 75 vll3 vll3 76 vll2 vll2 77 vll1 vll1 78 vcap2 vcap2 79 vcap1 vcap1 80 lcd_p24 lcd_p24 ptc4 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out lcd_p24 81 lcd_p25 lcd_p25 ptc5 spi0_sck lpt0_alt2 cmp0_out lcd_p25 82 lcd_p26/ cmp0_in0 lcd_p26/ cmp0_in0 ptc6 spi0_sout pdb0_extrg lcd_p26 83 lcd_p27/ cmp0_in1 lcd_p27/ cmp0_in1 ptc7 spi0_sin lcd_p27 84 lcd_p28/ adc1_se4b/ cmp0_in2 lcd_p28/ adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk i2s0_clkin lcd_p28 85 lcd_p29/ adc1_se5b/ cmp0_in3 lcd_p29/ adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_bcl k ftm2_flt0 lcd_p29 86 lcd_p30/ adc1_se6b/ cmp0_in4 lcd_p30/ adc1_se6b/ cmp0_in4 ptc10 i2c1_scl i2s0_rx_fs lcd_p30 87 lcd_p31/ adc1_se7b lcd_p31/ adc1_se7b ptc11 i2c1_sda i2s0_rxd lcd_p31 88 vss vss 89 vdd vdd 90 lcd_p36 lcd_p36 ptc16 can1_rx uart3_rx lcd_p36 91 lcd_p37 lcd_p37 ptc17 can1_tx uart3_tx lcd_p37 92 lcd_p38 lcd_p38 ptc18 uart3_rts_ b lcd_p38 93 lcd_p40 lcd_p40 ptd0 spi0_pcs0 uart2_rts_ b lcd_p40 94 lcd_p41/ adc0_se5b lcd_p41/ adc0_se5b ptd1 spi0_sck uart2_cts_ b lcd_p41 95 lcd_p42 lcd_p42 ptd2 spi0_sout uart2_rx lcd_p42 pinout k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 57 preliminary
100 qfp default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 96 lcd_p43 lcd_p43 ptd3 spi0_sin uart2_tx lcd_p43 97 lcd_p44 lcd_p44 ptd4 spi0_pcs1 uart0_rts_ b ftm0_ch4 ewm_in lcd_p44 98 lcd_p45/ adc0_se6b lcd_p45/ adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b ftm0_ch5 ewm_out_b lcd_p45 99 lcd_p46/ adc0_se7b lcd_p46/ adc0_se7b ptd6 spi0_pcs3 uart0_rx ftm0_ch6 ftm0_flt0 lcd_p46 100 lcd_p47 lcd_p47 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 lcd_p47 8.2 k40 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k40 sub-family data sheet data sheet, rev. 1, 11/2010. 58 preliminary freescale semiconductor, inc. preliminary
60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 adc1_dm1 adc1_dp1 adc0_dm1 adc0_dp1 vregin vout33 usb0_dm usb0_dp vss vdd pte6 pte5 pte4 pte3 pte2 pte1 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vll3 vss ptc3 ptc2 ptc1 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 ptb11 ptb10 ptb9 ptb8 ptb7 ptb3 ptb2 ptb1 ptb0 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6 vcap1 vcap2 vll1 vll2 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13 pta12 vss vdd pta5 pta4 pta3 pta2 pta1 pta0 pte26 pte25 pte24 vbat extal32 xtal32 dac0_out vref_out 98 ptd5 97 ptd4 96 ptd3 95 ptd2 94 ptd1 93 ptd0 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc4 ptc5 ptc6 81 82 83 ptc7 84 ptc8 85 ptc9 86 ptc10 87 ptc11 100 ptd7 figure 22. k40 100 lqfp pinout diagram 9 revision history the following table provides a revision history for this document. table 45. revision history rev. no. date substantial changes 1 11/2010 initial public revision revision history k40 sub-family data sheet data sheet, rev. 1, 11/2010. freescale semiconductor, inc. preliminary 59 preliminary
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